1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a function of controlling the output resistance of an output buffer circuit to a given value.
2. Description of the Background Art
The output resistance of an output buffer used in a semiconductor integrated circuit varies depending on factors such as variations in manufacture of MOS transistors (hereinafter, which may be simply referred to as "transistors") in the final stage in the output buffer, operating temperature, power-supply voltage, etc. Controlling the output resistance of the output buffer to a given value in operation of the LSI requires that the amount of current through the final-stage transistors in the output buffer be variably controllable (e.g., that the channel length or channel width of the transistors be variable) so that the amount of current can be appropriately corrected in accordance with the above-mentioned factors of variations.
FIG. 38 is an explanation diagram showing a conventional example of structure for realizing pull-down output resistance control and pull-up output resistance control of the output buffer. As shown in the diagram, an n-bit pull-up output resistance control signal SU and an n-bit pull-down output resistance control signal SD outputted from an output resistance control signal generating circuit 101 are inputted to control circuits 114 and 115 in at least one output resistance control output buffer 102 through a pull-up output resistance control signal line group 103 and a pull-down output resistance control signal line group 104, respectively. These output resistance control signals SU and SD cause the amount of current through the final-stage transistors 107 and 108 in the output buffer to vary for control of the output resistance.
FIG. 39 is a circuit diagram showing the output resistance control output buffer circuit 102 shown in FIG. 38 in more detail. As shown in this diagram, the final stage of the output buffer includes a group of NMOS transistors QUoff, QU0 to QU3 connected in parallel on the pull-up side. The group of transistors QUoff, QU0 to QU3 on the pull-up side have their respective drains connected to an power-supply (VDDQ) in common and their respective sources connected to an output pad 20 in common. It also includes NMOS transistors QDoff, QD0 to QD3 connected in parallel on the pull-down side. The group of transistors QDoff, QD0 to QD3 on the pull-down side have their respective sources grounded in common and their respective drains connected to the output pad 20 in common.
In this structure, the amount of current through the final-stage transistors on the pull-down side and the pull-up side in the output buffer, i.e., the output resistance is controlled with 4-bit binary signals respectively inputted to the gates of the transistors QD0 to QD3, QU0 to QU3.
In the transistors QD0 to QD3, the channel lengths are all equal and the channel widths W satisfy the relation of: 8.times.W(QD0)=4.times.W(QD1)=2.times.W(QD2)=W(QD3). Similarly, in the transistors QU0 to QU3, the channel lengths are all equal and the channel widths W satisfy the relation of: 8.times.W(QU0)=4.times.W(QU1)=2.times.W(QU2)=W(QU3).
The transistors QDoff and QUoff are provided as offsets so that the output pad will not go into a high-impedance state when the transistors QU0 to QU3, QD0 to QD3 are all turned off.
The 4-bit pull-down output resistance control signal SD (D3, D2, D1, D0) and the 4-bit pull-up output resistance control signal SU (U3, U2, U1, U0) outputted from the output resistance control signal generating circuit are inputted to the control circuits 114 and 115 for controlling the output resistance on the pull-down side and the pull-up side.
The pull-up bit control signals U0 to U3 in the pull-up output resistance control signal SU obtained through the pull-up output resistance control signal line group 103 are respectively provided to inputs of NAND gates 70 to 73. The outputs of the NAND gates 70 to 73 are respectively connected to the inputs of inverters 80 to 83 and the outputs from the inverters 80 to 83 are respectively provided to the gates of the transistors QU0 to QU3.
The pull-down bit control signals D0 to D3 in the pull-down output resistance control signal SD obtained through the pull-down output resistance control signal line group 104 are respectively provided to inputs of NAND gates 75 to 78. The outputs of the NAND gates 75 to 78 are respectively connected to the inputs of inverters 85 to 88 and the outputs from the inverts 85 to 88 are respectively provided to the gates of the transistors QD0 to QD3.
Data input DI is provided to a buffer 57, whose output is connected to an inverter 58. The output of the buffer 57 is connected to the other inputs of the NAND gates 70 to 73 in common and is also connected to the gate of the transistor QUoff. The output of the inverter 58 is connected to the other inputs of the NAND gates 75 to 78 in common and is also connected to the gate of the transistor QDoff.
In this structure, the pull-down output resistance control signal SD (D3, D2, D1, D0) and the pull-up output resistance control signal SU (U3, U2, U1, U0) cause the final-stage transistors QU0 to QU3 and QD0 to QD3 in the output buffer to turn on in varying combinations, so as to vary the output resistance.
FIG. 40 is a circuit diagram showing the output resistance control signal generating circuit 101 shown in FIG. 38 in more detail. As shown in this diagram, a pull-down output controlling transistor group includes NMOS transistors Q'D0 to Q'D3, Q'Doff. The transistors are sized (in channel length and channel width) equal to the transistors QD0 to QD3, QDoff used on the pull-down side in the output final stage in the output resistance control output buffer. Further, they are constructed in the same way as those on the pull-down size in the output final stage in the output resistance control output buffer, and their on-state resistance is controlled with a 4-bit binary signal. The sources of the group of pull-down side controlling transistors Q'Doff, Q'D0 to Q'D3 are grounded and their drains are connected to a pad 25 in common. The pad 25 is connected to a power-supply (VDDQ) through a resistance Rrefd.
Similarly, a pull-up output controlling transistor group includes transistors Q'U0 to Q'U3, Q'Uoff. The transistors are sized (in channel length and channel width) equal to the transistors QU0 to QU3, QUoff used on the pull-up side in the output final stage in the output resistance control output buffer. Further, they are constructed in the same way as those on the pull-up side in the output final stage in the output resistance control output buffer, and their on-state resistance is controlled with a 4-bit binary signal. The drains of the group of pull-up side controlling transistors Q'Uoff, Q'U0 to Q'U3 are connected to the power-supply (VDDQ) and their sources are connected to a pad 24 in common. The pad 24 is grounded through a resistance Rrefu.
A counter 116 outputs a 7-bit (Q0 to Q6) count value in synchronization with clock CLK. AND gates 141 to 144 respectively receive the count bits Q1 to Q4 at inputs and an AND gate 145 receives the count bits Q5 and Q6 at its one and the other input. The output of the AND gate 145 is connected to the other inputs of the AND gates 141 to 144 in common. AND gates 131 to 134 respectively receive the count bits Q1 to Q4 at inputs, and an AND gate 135 receives the count bits Q5 and Q6 at its one and the other input. The output of the AND gate 135 is connected to the other inputs of the AND gates 131 to 134 in common.
The counter 116 generates the 7-bit count value Q0 to Q6 and the AND gates 131 to 134 and the AND gates 141 to 144 provide outputs to control ON/OFF of the transistors Q'D0 to Q'D3 and the transistors Q'U0 to Q'U3 to vary the on-state resistance of the transistors.
The higher two bits (Q6, Q5) in the count value Q0 to Q6 specify a mode for controlling the pull-down output resistance, a mode for controlling the pull-up output resistance, or a mode for giving pause to the operation. That is to say, when both of the count bits Q5 and Q6 are at an "H" level, the AND gates 141 to 144 control the pull-down output resistance control signal, and when both of the count bits Q5 and Q6 are at an "L" level, the AND gates 131 to 134 control the pull-up output resistance control signal. When the count bit Q6 is at "H" and Q5 is at "L", and when Q6 is at "L" and Q5 is at "H," the operation pauses.
When the count bits Q5 and Q6 specify a mode for controlling the pull-down or pull-up output resistance, the on-state resistance of the transistors Q'U0 to Q'U3 or the transistors Q'D0 to Q'D3 varies in accordance with the lower second to fifth bits in the count value Q0 to Q6, i.e., the count bits Q1 to Q4.
The lowest one bit (Q0) in the count value Q0 to Q6 is used as timing clock for the output resistance control signal generating circuit 101.
Now, as shown in FIG. 41, the counter 116 has the function of counting m (&gt;7) bits. It outputs the higher seven bit in the m bits as the count value Q0 to Q6, performing the counting operation at frequency obtained by dividing the frequency of the clock CLK. The count value Q0 to Q6 from the counter 116 is made to vary at frequency sower than the frequency of the clock CLK to prevent excessive response to environmental variations due to disturbance. Accordingly, the output resistance control signals can be varied at frequency as low as several to tens of hertz.
A voltage PADup obtained from the pad 24 is provided to the positive input of a comparator 55 and a voltage PADdn obtained from the pad 25 is provided to the negative input of a comparator 56. A reference voltage Vrefd (Vrefu; Vrefd and Vrefu have the same value) obtained from a pad 30 is provided to the negative input of the comparator 55 and to the positive input of the comparator 56.
The output signal S55 from the comparator 55 is provided to the D input of a flip-flop 123 and the output signal S56 from the comparator 56 is provided to the D input of a flip-flop 124. The flip-flop 123 receives the count bit Q0 at its clock input and its Q output is connected to the clock input of a 4-bit flip-flop 121. The flip-flop 124 receives the count bit Q0 at its clock input and its Q output is connected to the clock input of a 4-bit flip-flop 122.
The 4-bit flip-flop 121 receives the count bits Q1 to Q4 at its D input and outputs the 4-bit pull-up output resistance control signal SU (the pull-up bit control signals U0 to U3) from its Q output. The 4-bit flip-flop 122 receives the count bits Q1 to Q4 at its D input and outputs the 4-bit pull-down output resistance control signal SD (the pull-down bit control signals D0 to D3) from its Q output.
In this structure, for the transistors Q'D0 to Q'D3 and Q'Doff in the pull-down output controlling transistor group, the transistors Q'D0 to Q'D3 can be ON/OFF controlled when the count bits Q6 and Q5 are both at the "H" level to vary the on-state resistance value Rdn of the entirety.
For example, when the count bits Q4 to Q1 are all at the "L" level, all the transistors except the offset transistor Q'Doff turn off. Accordingly, the on-state resistance value Rdn of the pull-down output controlling transistor group attains its maximum. Then the source-drain voltage PADdn of the pull-down output controlling transistor circuit, which is obtained from the pad 25 through voltage division with the resistance Rrefd connected to the power-supply, attains its maximum. When the count value Q0 to Q6 is counted up an Q4 to Q1 have all attained the "H" level, all of the transistors on the pull-down side, including the offset transistor Q'Doff, are turned on. Accordingly, the on-state resistance value Rdn of the pull-down output controlling transistor group attains its minimum. Then the source-drain voltage PADdn of the pull-down output controlling transistor circuit, which is obtained from the pad 25 through voltage division with the resistance Rrefd connected to the power-supply, attains its minimum.
FIG. 42 and FIG. 43 show the variation in the voltage PADdn obtained from the pad 25 with respect to the ground level in a period in which the count bits Q4 to Q1 go from all "L" to all "H." As shown in FIG. 42 and FIG. 43, the voltage PADdn gradually drops in steps, which becomes lower than the reference voltage Vrefd inputted to the comparator 56 when Q4 to Q1 provide a certain value.
The reference voltage Vrefd is set in advance so as to be equal to the voltage PADdn when the on-state resistance value Rdn of the pull-down output controlling transistor group attains a given output resistance value. Accordingly, the value of the count bits Q4 to Q1 obtained when the voltage PADdn becomes lower than the reference voltage Vrefd for the first time is provided to the output resistance control output buffer 102. The comparator 56 on the pull-down side compares the voltage PADdn and the reference voltage Vrefd and changes the signal S56 from "L" to "H" level when the former becomes lower than the latter. This signal S56 passes through one stage, the flip-flop 124, and then is provided to the clock input of the 4-bit flip-flop 122 that outputs the pull-down output resistance control signal SD to the output resistance control output buffer 102.
When the signal based on the signal S56 is provided to the clock input of the 4-bit flip-flop 122, the value of the count bits Q4 to Q1 presented when the voltage PADdn becomes lower than the reference voltage Vrefd is latched in the 4-bit flip-flop 122, and the 4-bit flip-flop 122 outputs the pull-down output resistance control signal SD from the Q output.
When the reference resistance Rrefd has a reference resistance value RD, the power-supply level connected to the reference resistance Rrefd is VDDQ, and the reference voltage is Vrefd, then the on-state resistance value Rdn of the pull-down side transistor group at this time is given by the equation (I) below: EQU Rdn=RD.multidot.Vrefd(VDDQ-Vrefd)-.DELTA.rd (I)
Since the on-state resistance value Rdn corresponds to the on-state resistance obtained when the potential of PADdn becomes lower than the reference voltage Vrefd for the firs time as shown in FIG. 43, it is smaller than the reference resistance value RD by the quantity corresponding to the difference by which the potential of the voltage PADdn is lower than the reference voltage Vrefd. This quantity is shown as .DELTA.rd in the equation (I). For example, If RD=50 (.OMEGA.), VDDQ=1.5 (V), and Vrefd=0.75 (V), then Rdn=50-.DELTA.rd (.OMEGA.).
Next, for the pull-up output controlling transistor group, the transistor Q'U0 to Q'U3 CIA be ON/OFF controlled when the count bits Q6 and Q5 are both at the "L" level to vary the on-state resistance value Rup of the entirety.
For example, when the count bits Q4 to Q1 are all at the "L" level, all the transistors except the off NMOS transitory Q'Uoff turn off. Accordingly, the on-state resistance value Rup of the pull-up output controlling transistor group attains its maximum. Then the drain-ground voltage PADup of the pull-up output controlling transistor group, which is obtained from the pad 24 through voltage division with the resistance Rrefu connected to the ground level, attains its minimum. When the counter 116 counts up until Q4 to Q1 all attain the "H" level, all of the NMOS transistors on the pull-up side, including the offset transistor Q'Uoff, are turned on. Accordingly, the on-state resistance value Rup of the pull-up output controlling transistor group attains its minimum. Then the drain-ground voltage PADup of the pull-up output controlling transistor group, which is obtained from the pad 24 through voltage division with the resistance Rrefu connected to the ground level, attains its maximum.
FIG. 44 and FIG. 45 show the variation in the voltage PADup obtained from the pad 24 with respect to the ground level in a period in which the count bits Q4 to Q1 go from all "L" to all "H." As shown in FIG. 44 and FIG. 45, the voltage PADup gradually increases in steps, which exceeds the reference voltage Vrefu inputted to the comparator 55 when Q4 to Q1 are at certain value. The reference voltage Vrefu is set in advance so as to be equal to the voltage PADup when the on-state resistance value Rup of the pull-up output controlling transistor group attains a given output resistance value. Accordingly, the value of the count bits Q4 to Q1 obtained when the reference voltage Vrefu is exceeded for the first time is provided to the output resistance control output buffer 102. The comparator 55 on the pull-up side compares the voltage PADup and the reference voltage Vrefu and changes the output signal S55 from "L" to "H" level when the former becomes higher than the latter. This change in the signal S55 passes through one stage, the flip-flop 123, and then is provided to the clock input of the 4-bit flip-flop 121 that outputs the pull-up output resistance control signal SU.
When the signal based on the signal S55 is provided to the clock input of the 4-bit flip-flop 121, the value of the count bits Q4 to Q1 presented when the voltage PADup exceeds the reference voltage Vrefu is latched in the 4-bit flip-flop 121, and the 4-bit flip-flop 121 outputs the pull-up output resistance control signal SU from the Q output to the output resistance control output buffer 102.
When the reference resistance Rrefu has a resistance value RU, the power-supply level connected on the drain side of the pull-up output controlling transistor group is VDDQ, and the reference voltage is Vrefu, then the on-state resistance value Rup at this time is given by the equation (II) below: EQU Rup=RU.multidot.(VDDQ-Vrefu)/Vrefu-.DELTA.ru (II)
Since the on-state resistance value Rup corresponds to the on-state resistance value obtained when the voltage PADup exceeds the reference voltage Vrefu for the first time as shown in FIG. 45, it is smaller than the reference resistance value RU by the quantity corresponding to the difference by which the voltage PADup is higher than the reference voltage Vrefu. This quantity is shown as .DELTA.ru in the equation (II). For example, if Rrefu=50 (.OMEGA.), VDDQ=1.5 (V), and Vrefu=0.75 (V), then Rup=50-.DELTA.ru (.OMEGA.).
The conventional semiconductor integrated circuit can control the output resistance of the output buffer so that it can always maintain a given value regardless of variations in manufacture of the transistors and variations in operating temperature and power-supply voltage, through the use of the output resistance control signal generating circuit 104 and the output resistance control output buffer 102 constructed as described above.
However, in the pull-up output resistance control signal SU and the pull-down output resistance control signal SD having a plurality of bits outputted from the output resistance control signal generating circuit 101, a skew will take place among bits due to performance of the driver for driving the pull-up output resistance control signal line group 103 and the pull-down output resistance control signal line group 104, and capacitance and resistance on the respective signal lines.
Now considered is the problem of the inter-bit skew in such a transmission system as shown in FIG. 46 in which the pull-down side output resistance control output buffer 102P in the output resistance control output buffer 102 determines the "L" level of the output through voltage division of the terminating resistance R3 on the transmission line 110 and the output resistance on the pull-down side of the final-stage transistors (the on-state resistance value Rdn) in the output resistance control output buffer.
For example, if a skew BS occurs among bits as shown in FIG. 47 when the 4-bit pull-down output resistance control signal SD (D3, D2, D1, D0) changes from (1, 0, 0, 0) to (0, 1, 1, 1), then (D3, D2, D1, D0)=(0, 0, 0, 0) in the period of the inter-bit skew BS. If such an output resistance control signal D0 to D3 is inputted to the control circuit 115 in the pull-down side output resistance control output buffer 102P shown in FIG. 46, a glitch G will occur in the data output DO obtained from the output pad 20 as shown in FIG. 47. This glitch G propagates on the transmission line 110 to degrade the transmission quality.
Even if it is assumed that such a skew will not occur among bits in the output resistance control signal in the transmission system shown in FIG. 46, if the 4-bit pull-down output resistance control signal SD (D3, D2, D1, D0) largely changes from (1, 0, 0, 0) to (0, 0, 1, 1) as shown in FIG. 48, the amount of current flowing through the pull-down side transistor group in the output buffer final stage will rapidly change. Then a glitch G will occur in the data output DO from the output pad 20 due to inductance component originated from the package of the LSI etc. Further, the potential variation .DELTA.V of DC type at the output pad 20 is large. These factors will degrade the transmission quality of the transmission system.
Moreover, as has been described so far, controlling the output resistance of the output buffer requires the multi-bit control signals SD and SU outputted from the output resistance control signal generating circuit 101. Although more precisely controlling it requires control signals with larger numbers of bits, it is not allowable to unnecessarily expand the control signals, since it will cause difficulty in physical pattern layout for constructing the output buffer, as will be describe later.
In DC test to the output buffer included in LSI test times, it is necessary to conduct a test to see whether the output resistance value of the output resistance control output buffer varies in accordance with a multi-bit output resistance control signal to represent an appropriate output resistance value. In the circuit structure shown in the conventional example, it is not possible to provide arbitrary output resistance control signals SD and SU to the output buffer circuits from outside.
Even if the circuitry is constructed to allow input of bits corresponding to the multi-bit output resistance control signals SD and SU from the outside to solve the problem, the LSI requires a corresponding number of input pins. This solution is not practical because the LSI then requires an increased number of input/output pins as a whole.
Further, when the above-mentioned test is carried out with the conventional structure, it is necessary to continuously input the clock CLK in the same way as in the normal operation. In the output resistance control signal generating circuit 104, the counter 116 performs the counting operation at frequency as low as several to tens of hertz for the output resistance control signals SD and SU to prevent excessive response to environmental variations due to disturbance. Accordingly, conducting a test, e.g., a function test, requires a huge pattern of clock input. This raises a problem when it exceeds the capacity of pattern memory of the tester, and also provides serious ill effects, such as an increase in test time.
Considered next is the physical pattern layout for distributing multi-bit output resistance control signals to individual output buffers on a conventional circuit structure. The output resistance control signal generating circuit 101 and the output resistance control output buffer 102 can also be applied to an output buffer portion in a bidirectional buffer circuit in which an input buffer circuit and an output buffer circuit are provided in the same region.
Generally, such a bidirectional buffer circuit region BA as includes a clock system control circuit region 153, e.g., a synchronous circuit for cluck used in logic circuits in the LSI, will take the layout structure as shown in FIG. 49.
A plurality of bidirectional buffer circuit regions BA are provided adjacent to each other to form a bidirectional buffer circuit region BAG3. The plurality of bidirectional buffer circuit regions BA have input/output pads 150 spaced at pitch PITCH.
Signals are provided to each clock system control circuit region 153 from a corresponding signal pin region 154 formed of a signal input portion for data input, block system control signal, etc. The clock system control circuit region 153 containing control circuits, such as a sync circuit for the clock (chiefly flip-flops), has complicated interconnecting structure.
Signals, e.g., a high-impedance control signal (a signal for controlling whether to bring the input/output pad 150 to high impedance), are provided from the clock system control circuit region 153 to the driver circuit region 151.
The driver circuit region 151 has circuitry equivalent to the control circuits 114 and 115 in the output resistance control output buffer 102 (refer to FIG. 39), which outputs control signals to the final-stage transistor region 160 on the basis of signals obtained from the clock system control circuit region 153 and others.
The pull-up transistor group 107 and the pull-down transistor group 108 in the final-stage transistor region 160 vary the output resistance with the control signals outputted from the driver circuit region 151 and output signals from the input/output pad 150 to the outside.
The input circuit region 152 provides control signals to the clock system control circuit region 153 on the basis of signals obtained from the input/output pad 150.
With the bidirectional buffer circuit region BA having this structure, the pull-up output resistance control signal SU and the pull-down output resistance control signal SD from the output resistance control signal generating circuit 101 are given to the internal driver circuit region 151 generally from the signal pin region 154.
However, since the clock system control circuit region 153 has complicated interconnections inside, it is very difficult in circuit pattern design to form internal interconnections for transmission of the pull-up output resistance control signal SU and the pull-down output resistance control signal SD in the bidirectional buffer circuit region BA without adversely affecting the circuitry in the clock system control circuit region 153. Further, it becomes more difficult as the arrangement pitch PITCH becomes smaller or as the output resistance control signals have a larger number of bits.
As described above, there has been the problem that it is difficult to supply output resistance control signals from the signal pin region 154 in the bidirectional buffer circuit region BA.